This invention relates to integrated circuit product and processes. More particularly, the invention relates to high performance Dynamic Random Access Memory (DRAM) chips and processes for making such chips.
Present processing of DRAM structures typically utilizes a thick sidewall oxidation after gate conductor etch. The sidewall oxidation improves array retention time by a stress relief anneal of the wafer, and also by developing a significant bird's beak at the transfer gate device edges. The extended oxidation reduces electric fields and potentially helps with ameliorating defect densities. Currently, extension and halo implants are then performed after the sidewall oxidation step, which necessitates increased energy implants and causes deeper junctions. The deeper junctions may not be desirable for all or some of the logic support devices that are often disposed adjacent to the DRAM array. Splitting sidewall oxidation into two steps does not provide an adequate solution since the dopants in the support logic devices are exposed to thermal processing of the DRAM array at elevated temperature, which causes diffusion of the dopants that still results in deep Junctions. Therefore, a process is desired wherein a DRAM array may be provided with a thick sidewall oxidation while providing for shallow junctions in some or all of the support logic devices.